Event Length: Approximately 30 minutes

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Pulse I-V testing offers a way to address two primary test challenges for leading technologies: charge trapping and self-heating. Charge trapping is one of the most significant technical hurdles preventing high k gate stacks from being successfully
implemented into CMOS processing. In addition, pulse I-V techniques are critical for isothermal testing of new transistor structures and Silicon-on-Insulator (SOI) configurations, where self-heating issues can make it difficult or impossible to
characterize devices properly. Fast pulse characterization can capture device response much faster than the characteristic charging or self-heating time, which makes it possible to obtain a trapping-free or isothermal device characterization for use in device modeling and reliability studies, as well as process verification.

Seminar participants will learn about:

• Common issues in characterizing transistor performance with a high k gate.
• The effect of charge trapping in high k gates on device modeling and reliability.
• Isothermal pulse I-V testing to address self-heating issues.
• Ultra-short pulse I-V technique to model transistor performance.
• Common practices to optimize ultra-short pulse I-V measurement

Dave Rubin is a Senior Industry Market Manager with the Semiconductor Business Team at Keithley Instruments, presents this seminar.